VLSI • VERIFICATION • RTL • FPGA • ASIC
Building hardware.
Understanding what happens after the RTL.
I build digital hardware and document the engineering decisions, debugging, verification and implementation results behind it.
RTL
↓
SIMULATION
↓
LINT
↓
SYNTHESIS
↓
TIMING / AREA / POWER
↓
NETLISTFEATURED
What I'm building
APB-Based SPI Master Controller
Parameterized Verilog RTL taken from architecture and simulation through lint, synthesis, timing, area and power analysis.
Open project →FPGA CNN Accelerator
Hardware architecture experiments around convolution, BRAM, DSP usage, throughput and resource trade-offs.
In progress →LATEST WRITING
Things I learned by building
How to Design an SPI Master Controller in Verilog RTL
Learn how to design an SPI Master Controller in synthesizable Verilog RTL, integrate APB, implement SPI timing, verify the design, debug synthesis warnings, and analyze timing, area and power.
I Thought My RTL Was Broken: Why Design Compiler Removed BAUD_RATE_DIV[0]
A practical synthesis-debugging story from an APB-based SPI Master Controller.
ENGINEERING NOTE
A waveform tells you it works.
Synthesis tells you what it becomes.
Projects are documented with the actual RTL, waveforms, reports and implementation observations behind them.