About

I’m Chhandak Roy, a VLSI-focused engineer interested in RTL design, FPGA architecture and ASIC implementation.

I like learning by building: turning specifications into hardware, debugging the unexpected behavior, and then understanding what the tools reveal about the implementation.

This site is where I keep the technical notes that come out of that process.

Areas I work on

• Verilog / RTL design
• Digital interfaces and controllers
• FPGA architecture and acceleration
• ASIC synthesis and timing analysis
• Hardware debugging and design optimization

Find the source

Most project pages link directly to the corresponding GitHub repository so the implementation can be inspected alongside the explanation.

GitHub: ChhandakRoy